In prior art floating gate cells, in particular ≧45 nm NAND flash memory generations, there was still sufficient space between adjacent cells to use control gates which extend into the space between the cells and hence are capacitively coupled to the floating gate via both the top wall and the side walls. The larger coupling arises from a larger area between the control gate and floating gate due to side wall of the floating gate and/or because the floating gate is extending over the active area. When a bias is applied to the control gate, the electric field in the top oxide is smaller than that in the bottom oxide. The current flowing from the floating gate to the control gate is suppressed and charge can accumulate on the floating gate. Hence, in conventional floating gate memories, the problem of programming and/or erasing saturation was not critical in view of the coupling ratio.
As a result of scaling, the conventional floating gate NAND cell evolves into a more planar structure with a thin floating gate because the space between the floating gates is disappearing and in order to reduce the capacitive interference between neighboring cells. This leads to a loss of the coupling factor, which gives rise to the problem of programming and/or erasing saturation: as a consequence of the planar structure, the current flowing from the floating gate to the control gate equals the current flowing from the substrate to the floating gate, so no charge can accumulate on the floating gate. Independent of the applied bias and the charge stored initially on the floating gate, the cell will evolve to the charge neutral state and no threshold VT-window can develop in such a cell. This phenomenon is known as programming/erase saturation. As long as the top and bottom oxides are thick enough so that they operate in the FN tunneling regime, changing the thickness of the top and/or bottom oxides will not fundamentally alter the situation. So this is a real problem which is faced in sub-32 nm generations NAND flash memory which lack sidewall capacitance due to the planar structure.
Other prior art is formed by JP 2000-299395, which discloses a non-volatile memory cell having a floating gate consisting of bottom p-type layer and a top n-type layer. This stack is believed to create an electrical field such that programmed electrons are kept away from the tunnel dielectric. This way charge retention might be improved.
Other prior art is formed by US 2007/0235793 which discloses a non-volatile memory cell having a floating gate consisting of a bottom layer and a top layer, the floating gate being separated from the semiconductor substrate by an insulating layer. The materials of the bottom layer and of the substrate are selected as to reduce the barrier for injection from the substrate into the bottom layer during programming while an increased barrier is formed for tunneling of stored carriers from the floating gate back to the substrate in the idle state. To this effect, the bottom layer is formed in a semiconductor material having a bandgap smaller than the bandgap of the semiconductor substrate. Alternatively, the bottom layer can be formed in a material having an electron affinity which is larger than the electron affinity of the semiconductor substrate. Preferably the bottom layer is a Ge-compound having a bandgap smaller than the silicon substrate. The stack is said to improve the injection of carriers into the floating gate during programming and to improve the charge retention of the programmed memory cell.